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o0709hkim 20090918-s00004 no.a1211-1/28 ver.1.02a lc87f2924b overview the sanyo lc87f2924b is an 8-bit microcomputer that, ce ntered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single ch ip a number of hardware features su ch as 26k-byte flash rom (onboard programmable), 768-byte ram, an on-chip debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit pwms), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, day an d time counter, a high-speed clock counter, a synchronous sio interface (with automatic block tran smission/reception capabilities), an asynch ronous/synchronous sio interface, a uart interface (full duplex), an 8-bit 13-channel ad converter, two 12-bit pwm channels, a system clock frequency divider, frequency variable rc oscillation circu it, and a 26-source 10-vect or interrupt feature. features ? flash rom ? on-board-programming with wide range, 3.0 to 5.5v, of voltage source. ? block-erasable in 128-byte units ? writable in 2-byte units ? 26624 8 bits ? ram ? 768 9 bits ? minimum bus cycle ? 83.3ns (12mhz) v dd =3.0 to 5.5v ? 125ns (8mhz) v dd =2.5 to 5.5v ? 250ns (4mhz) v dd =2.2 to 5.5v note: the bus cycle time here refers to the rom read speed. ordering number : ena1211a cmos ic from 26k byte, ram 768 byte on-chip 8-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
lc87f2924b no.a1211-2/28 ? minimum instruction cycle time ? 250ns (12mhz) v dd =3.0 to 5.5v ? 375ns (8mhz) v dd =2.5 to 5.5v ? 750ns (4mhz) v dd =2.2 to 5.5v ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1-bit units 59 (p0n, p1n, p2n, p30 to p33, p70 to p73, p80 to p86, pbn, pcn, pwm2, pwm3, cf2, xt2) (ports p30 to p33 are available in flga68k(6.0 6.0) package only.) ? normal withstand voltage input port 2 (cf1, xt1) ? reset pins 1 (res ) ? power pins 6 (v ss 1 to 3, v dd 1 to 3) ? timers ? timer 0: 16-bit timer/counter with two capture registers. mode 0: 8-bit timer with an 8-bit programmab le prescaler (with two 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programmabl e prescaler (with two 16-bit capture register) mode 3: 16-bit counter (with two 16-bit capture register) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-b it prescaler (with toggle outputs) + 8-bit timer/counter with an 8- bit prescaler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts are programmable in 5 different time schemes ? day and time counter 1) with a base timer, it can be used as 65535days + 23hours + 59minutes + 59seconds counter. 2) interrupts are programmable in 4 different time schemes (day, hour, minute or second). ? high-speed clock counter 1) can count clocks with a maximum clock rate of 20mhz (at a main clock of 10mhz) 2) can generate output real-time ? sio ? sio0: 8-bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle= 4/3 tcyc ) 3) automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8-data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8-data bits, stop detect)
lc87f2924b no.a1211-3/28 ? uart ? full duplex ? 7/8/9 bit data bits selectable ? 1 stop bit (2-bit in continuous data transmission) ? built-in baudrate generator ? ad converter: 8 bits 13 channels ? pwm: multifrequency 12-bit pwm 2 channels ? remote control receiver circuit (sharing pins with p73, int3, and t0in) ? noise rejection function (noise filter time constant selectable from 1 tcyc, 32 tcyc, and 128 tcyc) ? watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable ? clock output function 1) outputs clock with a frequency 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock of the system clock 2) outputs clock of the subclock ? interrupts ? 26 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x)) of multiplex interrupt cont rol. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/ bt0/bt1/dhmsc 5 00023h h or l t0h/int6 6 0002bh h or l t1l/t1h/int7 7 00033h h or l sio0/uart1 receive 8 0003bh h or l sio1/uart1 transmit 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/t4/t5/pwm2, pwm3 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? iflg (list of interrupt source flag function) 1) shows a list of interrupt source flags that caused a bran ching to a particular vector address (shown in the table above). ? subroutine stack levels: 384 levels (the stack is allocated in ram) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time)
lc87f2924b no.a1211-4/28 ? oscillation circuits ? rc oscillation circuit (internal): for system clock ? cf oscillation circuit: for system clock, with internal rf ? crystal oscillation circuit: for low-spee d system clock, with internal rf ? frequency variable rc oscillation circuit (internal): for system clock 1) adjustable in 4% (typ) step from a selected center frequency. 2) measures oscillation clock using a input signal from xt1 as a reference. ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz). ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of resetting the halt mode. (1) setting the reset pin to the low level (2) system resetting by watchdog timer (3) occurrence of an interrupt ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc, x?tal, and frequency variable rc oscillators automatically stop operation. 2) there are four ways of resetting the hold mode. (1) setting the reset pin to the low level. (2) system resetting by watchdog timer (3) having an interrupt source established at e ither int0, int1, int2, int4, int5, int6, or int7 * int0 and int1 hold mode reset is available only when level detection is set. (4) having an interrupt source established at port 0 ? x'tal hold mode: suspends instruction execution and the oper ation of the peripheral circuits except the base timer. 1) the cf, rc, and frequency variable rc oscillators automatically stop operation. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are six ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) system resetting by watchdog timer (3) having an interrupt source established at e ither int0, int1, int2, int4, int5, int6, or int7 * int0 and int1 hold mode reset is available only when level detection is set. (4) having an interrupt source established at port 0 (5) having an interrupt source established in the base timer circuit (6) having an interrupt source established in the day and time counter circuit ? on-chip debugger ? supports software debugging with the ic mounted on the target board (lc87d2932a). lc87f2924b has an on-chip debugger but its function is limited. ? package form ? qip64e (14 14): lead-free type ? tqfp64j (7 7): lead-free type ? flga68k (6.0 6.0): lead-free type ? flga64 (5.0 5.0): lead-free type ? development tools ? on-chip debugger: tcb87- typeb + lc87d2932a
lc87f2924b no.a1211-5/28 ? programming boards package programming boards qip64e (14 14) w87f50256q tqfp64j (7 7) w87f58256tq7 flga68k (6.0 6.0) w87f58256fl6 * this board is built to order. it may take about a month to deliver. flga64 (5.0 5.0) w87f59256fl5 * this board is built to order. it may take about a month to deliver. ? flash rom programmer maker model supported version device flash support group, inc. (fsg) single programmer af9708 af9709/af9709b/af9709c (including ando electric co., ltd. models) rev 02.82 or later lc87f2924b af9101/af9103(main body) (fsg models) flash support group, inc. (fsg) + sanyo (note 1) in-circuit programmer sib87(inter face driver) (sanyo model) (note 2) lc87f2924b single/gang programmer skk/skk type b (sanyo fws) sanyo in-circuit/gang programmer skk-dbg type b (sanyo fws) application version 1.04 or later chip data version 2.11 or later lc87f2924 note1: on-board-programmer from fsg (af9101/af9103) and serial interface driver from sanyo (sib87) together can give a pc-less, standalone on-board-programming capabilities. note2: it needs a special programming devices and applications depending on the use of programming environment. please ask fsg or sanyo for the information. package dimensions package dimensions unit : mm (typ) unit : mm (typ) 3159a 3289 sanyo : tqfp64j(7x7) 7.0 9.0 7.0 9.0 0.125 0.5 0.16 0.4 (0.5) (1.0) 1.2max 0.1 1 16 33 48 17 64 32 49 sanyo : qip64e(14x14) 14.0 17.2 14.0 17.2 0.15 0.35 0.8 (2.7) 3.0max 0.1 0.8 (1.0) 116 17 32 33 48 49 64
lc87f2924b no.a1211-6/28 pin assignment note: port p30, p31, p32, p33 are not available in the above package. sanyo: qip64e(14 14) ?lead-free type? sanyo: tqfp64j(7 7) ?lead-free type? top view 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 p83/an3 p84/an4 p85/an5 p86/an6 pc0/an8 pc1/an9 pc2/an10 pc3/an11 pc4 pc5/dbgp0 pc6/dbgp1 pc7/dbgp2 v dd 3 v ss 3 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 p27/int5/t1in/int7/t0hcp1 p26/int5/t1in/int6/t0lcp1 p25/int5/t1in p24/int5/t1in p23/int4/t1in p22/int4/t1in p21/urx/int4/t1in p20/utx/int4/t1in p07/t7o p06/t6o p70/int0/t0lcp p71/int1/t0hcp p72/int2/t0in p73/int3/t0in res xt1 xt2 v ss 1 cf1/an12 cf2/an13 v dd 1 p80/an0 p81/an1 p82/an2 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz pwm2 pwm3 v dd 2 v ss 2 p00 p01 p02 p03 p04 p05/cko lc87f2924b 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8910 11 12 13 14 15 16
lc87f2924b no.a1211-7/28 package dimensions unit : mm (typ) 3326 package dimensions unit : mm (typ) 3328 sanyo : flga68k(6.0x6.0) 6.0 0.5 0.5 top view side view bottom view 0.3 0.4 6.0 0.85max 0.0nom 0.5 (0.45) (0.45) 0.5 0.3 lkjhg fedcba 11 10 9 8 7 6 5 4 3 2 1 sanyo : flga64(5.0x5.0) 5.0 0.3 5.0 0.8 0.0nom 0.75 0.75 0.5 2 1345678 0.5 gfe dcba h
lc87f2924b no.a1211-8/28 pin assignments pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 p12/sck0 18 p06/t6o 35 pb1 52 p70/int0/t0lcp 2 p13/so1 19 p07/t7o 36 pb0 53 p71/int1/t0hcp 3 p14/si1/sb1 20 p20/utx/int4/t1in 37 v ss 3 54 p72/int2/t0in 4 p15/sck1 21 p21/urx/int4/t1in 38 v dd 3 55 p73/int3/t0in 5 p16/t1pwml 22 p22/int4/t1in 39 pc7/dbgp2 56 res 6 p17/t1pwmh/buz 23 p23/int4/t1in 40 pc6/dbgp1 57 xt1 7 pwm2 24 p24/int5/t1in 41 pc5/dbgp0 58 xt2 8 pwm3 25 p25/int5/t1in 42 pc4 59 v ss 1 9 v dd 2 26 p26/int5/t1in /int6/tolcp1 43 pc 3/an11 60 cf1/an12 10 v ss 2 27 p27/int5/t1in/int7/t0 hcp1 44 pc2/an10 61 cf2/an13 11 p00 28 pb7 45 pc1/an9 62 v dd 1 12 p01 29 pb6 46 pc0/an8 63 p80/an0 13 p02 30 pb5 47 p86/an6 64 p81/an1 14 p03 31 pb4 48 p85/an5 65 p82/an2 15 p04 32 pb3 49 p84/an4 66 p10/so0 16 p05/cko 33 pb2 50 p83/an3 67 p11/si0/sb0 17 p30 34 p31 51 p32 68 p33 note: a1, a11, l1, l11 are dummy terminals for the package. these terminals need to be bonded with foot pattern for the secure bonding of the package. sanyo: flga68k(6.0 6.0) ?lead-free type? top view 11 10 9 8 7 6 5 4 3 2 1 51 50 53 55 57 59 61 63 65 67 1 52 54 56 58 60 62 64 66 68 49 48 2 3 47 46 4 5 45 44 6 7 43 42 8 9 41 40 10 11 39 38 12 13 37 36 14 15 35 33 31 29 27 25 23 21 19 16 17 34 32 30 28 26 24 22 20 18 a b c d e f g h j k l lc87f2924b
lc87f2924b no.a1211-9/28 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 p12/sck0 17 p06/t6o 33 pb1 49 p70/int0/t0lcp 2 p13/so1 18 p07/t7o 34 pb0 50 p71/int1/t0hcp 3 p14/si1/sb1 19 p20/utx/int4/t1in 35 v ss 3 51 p72/int2/t0in 4 p15/sck1 20 p21/urx/int4/t1in 36 v dd 3 52 p73/int3/t0in 5 p16/t1pwml 21 p22/int4/t1in 37 pc7/dbgp2 53 res 6 p17/t1pwmh/buz 22 p23/int4/t1in 38 pc6/dbgp1 54 xt1 7 pwm2 23 p24/int5/t1in 39 pc5/dbgp0 55 xt2 8 pwm3 24 p25/int5/t1in 40 pc4 56 v ss 1 9 v dd 2 25 p26/int5/t1in/int6/t0lc p1 41 pc3/an11 57 cf1/an12 10 v ss 2 26 p27/int5/t1in/int7/t0 hcp1 42 pc2/an10 58 cf2/an13 11 p00 27 pb7 43 pc1/an9 59 v dd 1 12 p01 28 pb6 44 pc0/an8 60 p80/an0 13 p02 29 pb5 45 p86/an6 61 p81/an1 14 p03 30 pb4 46 p85/an5 62 p82/an2 15 p04 31 pb3 47 p84/an4 63 p10/so0 16 p05/cko 32 pb2 48 p83/an3 64 p11/si0/sb0 note: port p30, p31, p32, p33 are not available in the above package. sanyo: flga64(5.0 5.0) ?lead-free type? 48 50 52 53 58 61 2 1 a b c d e f g h 8 7 6 5 4 3 2 1 47 49 54 56 57 59 64 63 43 45 51 55 60 3 4 6 41 42 44 46 62 7 5 8 38 36 35 28 23 19 13 11 33 34 29 26 21 20 18 16 31 32 27 25 24 22 17 15 40 37 39 30 14 12 10 9 top view lc87f2924b
lc87f2924b no.a1211-10/28 system block diagram interrupt control standby control ir pla clock generator cf rc x?tal bus interface port 0 port 1 sio0 sio1 timer 0 timer 1 timer 4 timer 5 port 2 port 7 port 8 adc alu flash rom pc acc b register c register psw rar ram stack pointer watchdog timer base timer uart1 timer 6 int0 to 7 noise filter timer 7 port b port c on-chip debugger pwm2/3 vmrc port 3 day and time counter
lc87f2924b no.a1211-11/28 pin description pin name i/o description option v ss 1 v ss 2 v ss 3 - -power supply pin no v dd 1 v dd 2 v dd 3 - +power supply pin no port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? hold reset input ? port 0 interrupt input ? shared pins p05: clock output (system clock/can selected from sub clock) p06: timer 6 toggle output p07: timer 7 toggle output yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: timer 1pwml output p17: timer 1pwmh output/beeper output yes port 2 ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p20: uart transmit p21: uart receive p26: int6 input/hold reset input/timer 0l capture 1 input p27: int7 input/ hold reset i nput/timer 0h capture 1 input p20 to p23: int4 input/hold reset input/ timer 1 event input/timer 0l capture input/ timer 0h capture input p24 to p27: int5 input/hold reset input/ timer 1 event input/timer 0l capture input/ timer 0h capture input interrupt acknowledge type rising falling rising & falling h level l level int4 int5 int6 int7 enable enable enable enable enable enable enable enable enable enable enable enable disable disable disable disable disable disable disable disable p20 to p27 i/o yes port 3 p30 to p33 i/o ? 4-bit i/o port (these ports are available in flga68k(6.0 6.0) package only.) ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. yes continued on next page.
lc87f2924b no.a1211-12/28 continued from preceding page. pin name i/o description option port 7 ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p70: int0 input/hold reset input/time r 0l capture input/watchdog timer output p71: int1 input/hold reset i nput/timer 0h capture input p72: int2 input/hold reset input/timer 0 event input/timer 0l capture input/ high speed clock counter input p73: int3 input (with noise filter)/time r 0 event input/timer 0h capture input interrupt acknowledge type rising falling rising & falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable p70 to p73 i/o no port 8 p80 to p86 i/o ? 7-bit i/o port ? i/o specifiable in 1-bit units ? shared pins ad converter input port: an0 (p80) to an6 (p86) no pwm2 pwm3 i/o ? pwm2 and pwm3 output ports ? general-purpose i/o available no port b pb0 to pb7 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units. yes port c pc0 to pc7 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins ad converter input port: an8 (pc0) to an11 (pc3) on-chip debugger pins: dbgp0 to dbgp2 (pc5 to pc7) yes res input reset pin no xt1 input ? 32.768khz crystal oscillator input pin ? shared pins general-purpose input port no xt2 i/o ? 32.768khz crystal oscillator output pin ? shared pins general-purpose i/o port no cf1 input ? ceramic resonator input pin ? shared pins general-purpose input port ad converter input port: an12 no cf2 i/o ? ceramic resonator output pin ? shared pins general-purpose i/o port ad converter input port: an13 no
lc87f2924b no.a1211-13/28 on-chip debugger pin connection requirements for the treatment of the on-chip debugger pins, refer to the separately available documents entitled ?rd87 on-chip debugger installation manual? recommended unused pin connections recommended unused pin connections port name board software p00 to p07 open output low p10 to p17 open output low p20 to p27 open output low p30 to p33 open output low p70 to p73 open output low p80 to p86 open output low pwm2,pwm3 open output low pb0 to pb7 open output low pc0 to pc6 open output low pc7 pulled low with a 100k resistor or less. output disable xt1 pulled low with a 100k resistor or less - xt2 open output low cf1 pulled low with a 100k resistor or less - cf2 open output low port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable p00 to p07 1 bit 2 nch-open drain programmable 1 cmos programmable p10 to p17 1 bit 2 nch-open drain programmable 1 cmos programmable p20 to p27 1 bit 2 nch-open drain programmable 1 cmos programmable p30 to p33 1 bit 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable p80 to p86 - no nch-open drain no pwm2, pwm3 - no cmos no 1 cmos programmable pb0 to pb7 1 bit 2 nch-open drain programmable 1 cmos programmable pc0 to pc7 1 bit 2 nch-open drain programmable xt1 - no input for 32.768khz crystal oscillator (input only) no xt2 - no output for 32.768khz crystal oscillator (nch-open drain when in general-purpose output mode) no cf1 - no input for ceramic oscillator (input only) no cf2 - no output for ceramic oscillator (nch-open drain when in general-purpose output mode) no
lc87f2924b no.a1211-14/28 user option table option name option to be applied on flash-rom version option selected in units of option selection cmos p00 to p07 { 1 bit nch-open drain cmos p10 to p17 { 1 bit nch-open drain cmos p20 to p27 { 1 bit nch-open drain cmos p30 to p33 { 1 bit nch-open drain cmos pb0 to pb7 { 1 bit nch-open drain cmos port output type pc0 to pc7 { 1 bit nch-open drain 00000h program start address - { - 07e00h *1: connect the ic as shown below to minimize the noise input to the v dd 1 pin. be sure to electrically short the v ss 1, v ss 2, and v ss 3 pins. *2: the internal memory is sustained by v dd 1. if none of v dd 2 and v dd 3 are backed up, the high level output at the ports are unstable in the hold backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. make sure that the port outputs are held at the low level in the hold backup mode. power supply lsi v dd 1 for backup *2 v dd 2 v dd 3 v ss 3 v ss 2 v ss 1
lc87f2924b no.a1211-15/28 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 input voltage v i (1) xt1, cf1 -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2, 3, 7, 8 ports b, c pwm2, pwm3, xt2, cf2 -0.3 v dd +0.3 v ioph(1) ports 0, 1, 2, 3 ports b, c cmos output select per 1 applicable pin -10 ioph(2) pwm2, pwm3 per 1 applicable pin -20 peak output current ioph(3) p71 to p73 per 1 applicable pin -5 iomh(1) ports 0, 1, 2, 3 ports b, c cmos output select per 1 applicable pin -7.5 iomh(2) pwm2, pwm3 per 1 applicable pin -10 mean output current (note 1-1) iomh(3) p71 to p73 per 1 applicable pin -3 ioah(1) p71 to p73, p32 total of all applicable pins -10 ioah(2) port 1, p33 pwm2, pwm3 total of all applicable pins -25 ioah(3) ports 0, 2, p30 total of all applicable pins -25 ioah(4) ports 0, 1, 2, p30, pwm2, pwm3, p33 total of all applicable pins -45 ioah(5) port b, p31 total of all applicable pins -25 ioah(6) port c total of all applicable pins -25 high level output current total output current ioah(7) ports b, c, p31 total of all applicable pins -45 iopl(1) p02 to p07 ports 1, 2, 3, b, c pwm2, pwm3 per 1 applicable pin 20 iopl(2) p00, p01 per 1 applicable pin 30 peak output current iopl(3) ports 7, 8, xt2, cf2 per 1 applicable pin 10 ioml(1) p02 to p07 ports 1, 2, 3, b, c pwm2, pwm3 per 1 applicable pin 15 ioml(2) p00, p01 per 1 applicable pin 20 mean output current (note 1-1) ioml(3) ports 7, 8 xt2, cf2 per 1 applicable pin 7.5 ioal(1) port 7, p32 p83 to p86, xt2, cf2 total of all applicable pins 15 ioal(2) p80 to p82 total of all applicable pins 15 ioal(3) ports 7, 8, p32 xt2, cf2 total of all applicable pins 20 ioal(4) port 1, p33 pwm2, pwm3 total of all applicable pins 45 ioal(5) ports 0, 2, p30 total of all applicable pins 45 ioal(6) ports 0, 1, 2 p30, p33 pwm2, pwm3 total of all applicable pins 80 ioal(7) port b, p31 total of all applicable pins 45 ioal(8) port c total of all applicable pins 45 low level output current total output current ioal(9) ports b, c, p31 total of all applicable pins 80 ma note 1-1: the mean output current is a mean value measured over 100ms. continued on next page.
lc87f2924b no.a1211-16/28 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit qip64e(14 14) 292 tqfp64j(7 7) 133 flga68k(6.0 6.0) 96 power dissipation pd max flga64(5.0 5.0) ta=-40 to +85 c 91 mw operating ambient temperature topr -40 +85 storage ambient temperature tstg -55 +125 c allowable operating range at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit 0.245s tcyc 200s 3.0 5.5 0.367s tcyc 200s 2.5 5.5 operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2=v dd 3 0.681s tcyc 200s 2.2 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode. 2.0 5.5 v ih (1) ports 1, 2 p71 to p73 p70 port input/ interrupt side 2.2 to 5.5 0.3v dd +0.7 v dd v ih (2) ports 0, 3, 8, b, c pwm2, pwm3 2.2 to 5.5 0.3v dd +0.7 v dd v ih (3) port 70 watchdog timer side 2.2 to 5.5 0.9v dd v dd high level input voltage v ih (4) xt1, xt2, cf1, cf2, res 2.2 to 5.5 0.75v dd v dd 4.0 to 5.5 v ss 0.1v dd +0.4 v il (1) ports 1, 2 p71 to p73 p70 port input/ interrupt side 2.2 to 4.0 v ss 0.2v dd 4.0 to 5.5 v ss 0.15v dd +0.4 v il (2) ports 0, 3, 8, b, c pwm2, pwm3 2.2 to 4.0 v ss 0.2v dd v il (3) port 70 watchdog timer side 2.2 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (4) xt1, xt2, cf1, cf2, res 2.2 to 5.5 v ss 0.25v dd v 3.0 to 5.5 0.245 200 2.5 to 5.5 0.367 200 instruction cycle time (note 2-2) tcyc 2.2 to 5.5 0.681 200 s 3.0 to 5.5 0.1 12 2.5 to 5.5 0.1 8 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty =50 5% 2.2 to 5.5 0.1 4 3.0 to 5.5 0.2 24.4 2.5 to 5.5 0.2 16 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division ratio=1/2 2.2 to 5.5 0.2 8 mhz note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. continued on next page.
lc87f2924b no.a1211-17/28 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit fmcf(1) cf1, cf2 ? 12mhz ceramic oscillation ? see fig. 1. 3.0 to 5.5 12 fmcf(2) cf1, cf2 ? 8mhz ceramic oscillation ? see fig. 1. 2.5 to 5.5 8 fmcf(3) cf1, cf2 ? 4mhz ceramic oscillation ? see fig. 1. 2.2 to 5.5 4 fmrc internal rc oscillation 2.2 to 5.5 0.3 1.0 2.0 fmvmrc(1) ? frequency variable rc source oscillation ? when vmraj2 to 0=4, vmfaj2 to 0=0, vmsl4m=0 2.2 to 5.5 10 fmvmrc(2) ? frequency variable rc source oscillation ? when vmraj2 to 0=4, vmfaj2 to 0=0, vmsl4m=1 2.2 to 5.5 4 mhz oscillation frequency range (note 2-3) fsx?tal xt1, xt2 ? 32.768khz crystal oscillation ? see fig. 2. 2.2 to 5.5 32.768 khz opvmrc(1) when vmsl4m=0 2.2 to 5.5 8 10 12 frequency variable rc oscillation usable range opvmrc(2) when vmsl4m=1 2.2 to 5.5 3.5 4 4.5 mhz vmadj(1) each step of vmrajn (wide range) 2.2 to 5.5 8 24 64 frequency variable rc oscillation adjustment range vmadj(2) each step of vmfajn (small range) 2.2 to 5.5 1 4 8 % note 2-3: see tables 1 and 2 for the oscillation constants.
lc87f2924b no.a1211-18/28 electrical characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2, 3 ports 7, 8 ports b, c res pwm2, pwm3 output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.2 to 5.5 1 i ih (2) xt1, xt2, cf1, cf2 for input port specification v in =v dd 2.2 to 5.5 1 high level input current i ih (3) cf1 v in =v dd 2.2 to 5.5 15 i il (1) ports 0, 1, 2, 3 ports 7, 8 ports b, c res pwm2, pwm3 output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.2 to 5.5 -1 i il (2) xt1, xt2, cf1, cf2 for input port specification v in =v ss 2.2 to 5.5 -1 low level input current i il (3) cf1 v in =v ss 2.2 to 5.5 -15 a v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) ports 0, 1, 2, 3 ports b, c i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (4) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (5) p71 to p73 i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (6) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (7) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 high level output voltage v oh (8) pwm2, pwm3 i oh =-1ma 2.2 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.6ma 3.0 to 5.5 0.4 v ol (3) ports 0, 1, 2, 3 ports b, c pwm2, pwm3 i ol =1ma 2.2 to 5.5 0.4 v ol (4) i ol =1.6ma 3.0 to 5.5 0.4 v ol (5) ports 7, 8 xt2, cf2 i ol =1ma 2.2 to 5.5 0.4 v ol (6) i ol =30ma 4.5 to 5.5 1.5 v ol (7) i ol =5ma 3.0 to 5.5 0.4 low level output voltage v ol (8) p00, p01 i ol =2.5ma 2.2 to 5.5 0.4 v rpu(1) 4.5 to 5.5 15 35 80 pull-up resistance rpu(2) ports 0, 1, 2, 3 ports 7, b, c v oh =0.9v dd 2.2 to 5.5 18 50 150 k hysteresis voltage vhys res ports 1, 2, 7 2.2 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 2.2 to 5.5 10 pf
lc87f2924b no.a1211-19/28 serial input/output characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 6. 1 input clock high level pulse width tsckha(1) sck0(p12) ? continuous data transmission/reception mode ? see fig. 6. ? (note 4-1-2) 2.2 to 5.5 4 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig. 6. 1/2 tsck serial clock output clock high level pulse width tsckha(2) sck0(p12) ? continuous data transmission/reception mode ? cmos output selected ? see fig. 6. 2.2 to 5.5 tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tcyc data setup time tsdi(1) 2.2 to 5.5 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.2 to 5.5 0.03 tdd0(1) ? continuous data transmission/reception mode ? (note 4-1-3) 2.2 to 5.5 (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 2.2 to 5.5 1tcyc +0.05 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11) (note 4-1-3) 2.2 to 5.5 (1/3)tcyc +0.15 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
lc87f2924b no.a1211-20/28 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig. 6. 2.2 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected ? see fig. 6. 2.2 to 5.5 1/2 tsck data setup time tsdi(2) 2.2 to 5.5 0.03 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.2 to 5.5 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.2 to 5.5 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use.
lc87f2924b no.a1211-21/28 pulse input conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72), int3(p73) when noise filter not used, int4(p20 to p23), int5(p24 to p27), int6(p26), int7(p27) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.2 to 5.5 1 tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 256 tcyc high/low level pulse width tpil(5) res resetting is enabled. 2.2 to 5.5 200 s ad converter characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 15.68 (tcyc= 0.49s) 97.92 (tcyc= 3.06s) ad conversion time=32 tcyc (when adcr2=0) (note 6-2) 3.0 to 5.5 21.8 (tcyc= 0.681s) 97.92 (tcyc= 3.06s) 4.5 to 5.5 18.82 (tcyc= 0.294s) 97.92 (tcyc= 1.53s) conversion time tcad ad conversion time=64 tcyc (when adcr2=1) (note 6-2) 3.0 to 5.5 43.6 (tcyc= 0.681s) 97.92 (tcyc= 1.53s) s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl an0(p80) to an6(p86), an8(pc0), an9(pc1), an10(pc2), an11(pc3), an12(cf1), an13(cf2) vain=v ss 3.0 to 5.5 -1 a note 6-1: the quantization erro r (1/2lsb) is excluded from the absolute accuracy value. note 6-2: the conversion time refers to the interval from th e time the instruction for starting the converter is issued to the time the complete digital value corresponding to the analog input value is loaded in the required register.
lc87f2924b no.a1211-22/28 consumption current characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddop(1) 4.5 to 5.5 8.3 20.9 iddop(2) ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 3.0 to 3.6 4.8 11.9 iddop(3) 4.5 to 5.5 6.3 15.7 iddop(4) 3.0 to 3.6 3.6 9.1 iddop(5) ? fmcf=8mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.5 to 3.0 2.4 7.1 iddop(6) 4.5 to 5.5 2.4 6 iddop(7) 3.0 to 3.6 1.3 3.3 iddop(8) ? fmcf=4mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 0.86 2.5 iddop(9) 4.5 to 5.5 0.75 3.1 iddop(10) 3.0 to 3.6 0.4 1.7 iddop(11) ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 0.28 1.35 iddop(12) 4.5 to 5.5 8 20 iddop(13) ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? internal rc oscillation stopped. ? system clock set to 10mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 3.0 to 3.6 4.7 12 iddop(14) 4.5 to 5.5 4.5 11.5 iddop(15) 3.0 to 3.6 2.6 6.6 iddop(16) ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? internal rc oscillation stopped. ? system clock set to 4mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 2.2 to 3.0 1.7 5 ma iddop(17) 4.5 to 5.5 35 115 iddop(18) 3.0 to 3.6 18 65 normal mode consumption current (note 7-1) iddop(19) v dd 1 =v dd 2 =v dd 3 ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 12 46 a note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page.
lc87f2924b no.a1211-23/28 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddhalt(1) 4.5 to 5.5 3.6 8.2 iddhalt(2) ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 3.0 to 3.6 2 4.6 iddhalt(3) 4.5 to 5.5 2.6 5.9 iddhalt(4) 3.0 to 3.6 1.4 3.3 iddhalt(5) ? halt mode ? fmcf=8mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.5 to 3.0 1 2.5 iddhalt(6) 4.5 to 5.5 1.15 2.65 iddhalt(7) 3.0 to 3.6 0.6 1.5 iddhalt(8) ? halt mode ? fmcf=4mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 0.4 1.1 iddhalt(9) 4.5 to 5.5 0.37 1.3 iddhalt(10) 3.0 to 3.6 0.2 0.75 iddhalt(11) ? halt mode ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 0.13 0.54 iddhalt(12) 4.5 to 5.5 3.6 8.2 iddhalt(13) ? halt mode ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? internal rc oscillation stopped. ? system clock set to 10mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 3.0 to 3.6 2 4.6 iddhalt(14) 4.5 to 5.5 1.7 4 iddhalt(15) 3.0 to 3.6 1 2.5 iddhalt(16) ? halt mode ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? internal rc oscillation stopped. ? system clock set to 4mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 2.2 to 3.0 0.7 1.8 ma iddhalt(17) 4.5 to 5.5 18.5 68 iddhalt(18) 3.0 to 3.6 10 38 halt mode consumption current (note 7-1) iddhalt(19) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=0hz (oscillation stopped) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.2 to 3.0 6.5 26 iddhold(1) 4.5 to 5.5 0.05 20 iddhold(2) 3.0 to 3.6 0.03 12 hold mode consumption current iddhold(3) ? hold mode ? cf1=v dd or open (external clock mode) 2.2 to 3.0 0.02 8 iddhold(4) 4.5 to 5.5 16 58 iddhold(5) 3.0 to 3.6 8.5 32 timer hold mode consumption current iddhold(6) v dd 1 ? timer hold mode ? cf1=v dd or open (external clock mode) ? fsx?tal=32.768khz crystal oscillation mode 2.2 to 3.0 5 20 a note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors.
lc87f2924b no.a1211-24/28 f-rom programming characteristics at ta = -10c to +55c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? without cpu current 3.0 to 5.5 5 10 ma tfw(1) ? erasing 20 30 ms programming time tfw(2) ? programming 3.0 to 5.5 40 60 s uart (full duplex) operating conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit transfer rate ubr utx(p20), urx(p21) 2.2 to 5.5 16/3 8192/3 tcyc data length: 7, 8, and 9 bits (lsb first) stop bits: 1 bit (2-bit in continuous data transmission) parity bits: none example of continuous 8-bit data transmission mode processing (first transmit data=55h) example of continuous 8-bit da ta reception mode processing (first receive data=55h) transmit data (lsb first) start of transmission end of transmission ubr start bit stop bit stop bit end of reception ubr receive data (lsb first) start of reception start bit
lc87f2924b no.a1211-25/28 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rf1 [ ] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz murata cstce12m0g52-r0 (10) (10) open 680 3.0 to 5.5 0.05 0.15 internal c1, c2 cstce8m00g52-r0 (10) (10) open 1k 2.5 to 5.5 0.13 0.4 8mhz murata cstls8m00g53-b0 (15) (15) open 1k 2.5 to 5.5 0.12 0.4 internal c1, c2 cstcr4m00g53-r0 (15) (15) open 2.2k 2.2 to 5.5 0.07 0.2 4mhz murata cstls4m00g53-b0 (15) (15) open 2.2k 2.2 to 5.5 0.05 0.15 internal c1, c2 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 4). characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a sanyo- designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator circuit constant oscillation stabilization time nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf2 [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyocom mc-306 18 18 open 560k 2.2 to.5.5 1.3 3.0 applicable cl value= 12.5pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see figure 4). note: the components that are involved in oscillation should be placed as close to the ic and to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit figure 3 ac timing measurement point 0.5v dd cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf2 c1 rd1 c2 cf rf1
lc87f2924b no.a1211-26/28 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization times operating v dd lower limit power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd 0v internal rc oscillation cf1, cf2 xt1, xt2 state hold reset signal hold reset signal valid tmscf tmsx?tal hold halt hold reset signal absent
lc87f2924b no.a1211-27/28 figure 5 reset circuit figure 6 serial i/o waveforms figure 7 pulse input timing signal waveform c res v dd r res res note: determine the value of c res and r res so that the reset signal is present for a period of 200 s after the supply voltage goes beyond the lower limit of the ic?s operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transfer period (sio0 only) data ram transfer period (sio0 only)
lc87f2924b no.a1211-28/28 ps this catalog provides information as of september, 2009. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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